Includes index.

Machine generated contents note: ch. 1 Introduction to the Cortex-M Processor Family -- Cortex Profiles -- Cortex-M3 -- Advanced Architectural Features -- Cortex-M0 -- Cortex-M0+ -- Cortex-M4 -- DSP Instructions -- ch. 2 Developing Software for the Cortex-M Family -- Introduction -- Keil Microcontroller Development Kit -- The Tutorial Exercises -- Installation -- Exercise Building a First Program -- The Blinky Project -- Register Window -- Disassembly Window -- Project Configuration -- Hardware Debug -- ch. 3 Cortex-M Architecture -- Introduction -- Cortex-M Instruction Set -- Programmer's Model and CPU Registers -- Program Status Register -- Q Bit and Saturated Math Instructions -- Interrupts and Multicycle Instructions -- Conditional Execution---IF THEN Blocks -- Exercise: Saturated Math and Conditional Execution -- Cortex-M Memory Map and Busses -- Write Buffer -- Memory Barrier Instructions -- System Control Block -- Bit Manipulation -- Exercise: Bit Banding --

Contents note continued: Dedicated Bit Manipulation Instructions -- Systick Timer -- Nested Vector Interrupt Controller -- Operating Modes -- Interrupt Handling---Entry -- Interrupt Handling---Exit -- Interrupt Handling---Exit: Important! -- Exercise: Systick Interrupt -- Cortex-M Processor Exceptions -- Usage Fault -- Bus Fault -- Memory Manager Fault -- Hard Fault -- Enabling Fault Exceptions -- Priority and Preemption -- Groups and Subgroups -- Run Time Priority Control -- Exception Model -- NVIC Tail Chaining -- NVIC Late Arriving -- NVIC POP Preemption -- Exercise: Working with Multiple Interrupts -- Bootloader Support -- Exercise: Bootloader -- Power Management -- Entering Low-Power Modes -- Configuring the Low-Power Modes -- Exercise: Low-Power Modes -- Moving from the Cortex-M3 -- Cortex-M4 -- Cortex-M0 -- Cortex-M0+ -- ch. 4 Cortex Microcontroller Software Interface Standard -- Introduction -- CMSIS Specifications -- CMSIS Core -- CMSIS RTOS -- CMSIS DSP --

Contents note continued: CMSIS SVD and DAP -- Foundations of CMSIS -- Coding Rules -- MISRA C -- CMSIS Core Structure -- Startup Code -- System Code -- Device Header File -- CMSIS Core Header Files -- Interrupts and Exceptions -- Exercise: CMSIS and User Code Comparison -- CMSIS Core Register Access -- CMSIS Core CPU Intrinsic Instructions -- Exercise: Intrinsic Bit Manipulation -- CMSIS SIMD Intrinsics -- CMSIS Core Debug Functions -- Exercise: Simple ITM -- ch. 5 Advanced Architecture Features -- Introduction -- Cortex Processor Operating Modes -- Exercise: Stack Configuration -- Supervisor Call -- Exercise: SVC -- Pend_SVC Exception -- Example: Pend_SVC -- Interprocessor Events -- Exclusive Access -- Exercise: Exclusive Access -- Memory Protection Unit -- Configuring the MPU -- Exercise: MPU Configuration -- MPU Subregions -- MPU Limitations -- AHB Lite Bus Interface -- ch. 6 Developing with CMSIS RTOS -- Introduction -- Getting Started -- Setting Up a Project --

Contents note continued: First Steps with CMSIS RTOS -- Threads -- Starting the RTOS -- Exercise: A First CMSIS RTOS Project -- Creating Threads -- Exercise: Creating and Managing Threads -- Thread Management and Priority -- Exercise: Creating and Managing Threads II -- Multiple Instances -- Exercise: Multiple Thread Instances -- Build the Code and Start the Debugger -- Time Management -- Time Delay -- Waiting for an Event -- Exercise: Time Management -- Virtual Timers -- Exercise: Virtual Timer -- Idle Demon -- Exercise: Idle Thread -- Interthread Communication -- Signals -- Exercise: Signals -- RTOS Interrupt Handling -- Exercise: Interrupt Signal -- Run the Code -- Exercise: CMSIS RTX and SVC Exceptions -- Semaphores -- Exercise: Semaphore Signaling -- Using Semaphores -- Signaling -- Multiplex -- Exercise: Multiplex -- Rendezvous -- Exercise: Rendezvous -- Barrier Turnstile -- Exercise: Semaphore Barrier -- Semaphore Caveats -- Mutex -- Exercise: Mutex -- Mutex Caveats --

Contents note continued: Data Exchange -- Message Queue -- Exercise: Message Queue -- Memory Pool -- Mail Queue -- Exercise: Mailbox -- Configuration -- Thread Definition -- System Timer Configuration -- Timeslice Configuration -- Scheduling Options -- Preemptive Scheduling -- Round-Robin Scheduling -- Round-Robin Preemptive Scheduling -- Cooperative Multitasking -- Priority Inversion -- Exercise: Priority Inversion -- ch. 7 Practical DSP for the Cortex-M4 -- Introduction -- Cortex-M4 Hardware Floating Point Unit -- FPU Integration -- FPU Registers -- Enabling the FPU -- Exceptions and the FPU -- Using the FPU -- Exercise: Floating Point Unit -- Start the Debugger -- Cortex-M4 DSP and SIMD Instructions -- Exercise: SIMD Instructions -- Exercise: Optimizing DSP Algorithms -- The CMSIS DSP Library -- CMSIS DSP Library Functions -- Exercise: Using the Library -- DSP Data Processing Techniques -- Exercise: FIR Filter with Block Processing -- Fixed Point DSP with Q Numbers --

Contents note continued: Exercise: Fixed Point FFT -- Designing for Real-Time Processing -- Buffering Techniques: The Double or Circular Buffer -- Buffering Techniques: FIFO Message Queue -- Balancing the Load -- Exercise: RTX IIR -- Shouldering the Load, the Direct Memory Access Controller -- ch. 8 Debugging with CoreSight -- Introduction -- CoreSight Hardware -- Debugger Hardware -- CoreSight Debug Architecture -- Exercise: CoreSight Debug -- Hardware Configuration -- Software Configuration -- Debug Limitations -- Instrumentation Trace -- Exercise: Setting Up the ITM -- Software Testing Using the ITM with RTX RTOS -- Error Task -- Software Test Task -- Exercise: Software Testing with the ITM -- Instruction Trace with the ETM -- Exercise: Using the ETM Trace -- System Control Block Debug Support -- Tracking Faults -- Exercise: Processor Fault Exceptions -- CMSIS SVD -- Exercise: CMSIS SVD -- CMSIS DAP -- Cortex-M0+ MTB -- Exercise: MTB -- Debug Features Summary.